The present invention relates, in general, to the field of integrated circuit (xe2x80x9cICxe2x80x9d) memory devices. More particularly, the present invention relates to an integrated clocking latency and multiplexer control technique for double data rate (xe2x80x9cDDRxe2x80x9d) synchronous dynamic random access memory (xe2x80x9cSDRAMxe2x80x9d) device data paths.
SDRAM memory devices function somewhat differently than conventional random access memory devices such as DRAM and take advantage of the fact that most computer system memory access are, in fact, sequential. Consequently, SDRAM devices are designed to fetch the initial and ensuing data bits in a burst as quickly as possible. An on-chip burst counter allows the column portion of the address to be incremented rapidly in order to significantly speed retrieval of information in sequential read operations. The associated memory controller furnishes the first column address location and size of the block of memory to be accessed and the SDRAM memory device itself provides the read out bits as fast as the central processing unit (xe2x80x9cCPUxe2x80x9d) can take them, utilizing a clock to synchronize the timing between the CPU and memory device. In DDR SDRAM devices, this first column address location is supplied on the rising edge of the clock. However, the address for the data to be output on the falling edge of the clock may be obtained at this point in time in high-speed devices in order to be able to meet the data frequency requirements.
Historically, in order to synchronize data transfers among system logic devices, data transfers to/from conventional DRAM devices would be initiated on either the rising (the transition from logic level xe2x80x9czeroxe2x80x9d to xe2x80x9conexe2x80x9d) or falling (the transition from logic level xe2x80x9conexe2x80x9d to xe2x80x9czeroxe2x80x9d) edge of a clock signal. DDR SDRAM memory devices differ from conventional SDRAM by enabling output operations to occur on both the rising and falling edges of the clock, thereby effectively doubling the device""s output frequency without increasing the actual clock frequency.
In conventional DDR SDRAM designs, the data read out of the device is clocked out utilizing the system clock. In addition, multiple input/output (xe2x80x9cI/Oxe2x80x9d) configuration changes are also generally handled with a separate circuit, that is, one each to provide a X4, X8, X16 or other configurations. Moreover, in conventional designs, changes in xe2x80x9creadxe2x80x9d latency are often handled by providing entirely separate data paths. Still further, combining several modes of operation and differing functions into a single data path design could readily lead to a very complicated design that is also extremely slow.
Disclosed herein is an integrated clocking latency and multiplexer control technique for DDR SDRAM device data paths in which the clocking, control of the various I/O configurations and implementation of the various latencies are completely integrated. This further results in a robust and extremely efficient method of implementing all these functions which is easily transportable to other memory device designs.
In a particular embodiment disclosed herein, the xe2x80x9creadxe2x80x9d data pipeline is divided into as many portions as necessary to support the maximum latency of the device, which, in the example given, is three clock cycles following assertion of a xe2x80x9creadxe2x80x9d command. A particular clock signal is assigned to each stage of the pipeline, and for DDR memory devices, everything shifts on the one half cycle.
The first clock signal in the xe2x80x9creadxe2x80x9d pipeline is assigned to fetch data from the proper bank of the memory array. The order is preferential, since dealing with data from multiple banks in parallel would result in the requirement of many more data lines. The second clock signal is assigned to only fetch the proper data based on the I/O configuration of the part, that is, if the part is a X4 device, and the maximum configuration is X16, a 1 of 4 selection must be performed. The third and fourth clock signals are assigned to effectuate the odd/even sorting in preparing the data to be read out in a conventional DDR fashion. At this point, more clock signals can be added as necessary to achieve the desired latency. In the representative embodiment disclosed herein, a fifth clock signal is also disclosed. In the use of the technique of the present invention, the xe2x80x9cpositionxe2x80x9d and logic used to generate the above clock signals is what changes to achieve the various latencies and the data path itself does not change.
Particularly disclosed herein is an integrated circuit memory device comprising at least one memory bank, the memory bank being logically partitioned into even and odd portions thereof. Even and odd data buses are provided, the even and odd portions of the memory bank being selectively couplable to the even and odd data buses respectively for placing read data thereon by means of corresponding first multiplexers in response to a first control signal. A read pipeline sorting block is coupled to the even and odd data buses for selectively applying the read data on the even data bus to either of a rising or falling edge data output bus and the read data on the odd data bus to an opposite one of the rising or falling edge data output buses. In a particular embodiment disclosed herein, the memory device may further comprise a write pipeline sorting block coupled to the rising and falling edge data buses for receiving write data thereon, the write pipeline sorting block for selectively applying the write data on the rising edge data bus to either of the even or odd data buses and the write data on the falling edge data bus to an opposite one of the even or odd data buses.